Power semiconductors are commonly used in various application fields. A device having a power semiconductor is controlled by a low-power circuit operated with several tens of volts or below. This low-voltage circuit may control a high-voltage-driven circuit that is operated with several hundreds of volts and provides high-voltage power to another electronic device. Therefore, such a circuit has a low side region and a high side region.
The high side region of an integration circuit is electrically insulated from the low side region by insulation junction. A low-voltage signal is level-shifted to higher voltage by a level shift transistor so that a low-voltage control signal is suitable for a high-voltage element.
That is, a high voltage integration circuit according to the related art is divided into a high side region and a level shifter. The high side region represents a region floated to high voltage, and the level shifter serves to transmit a signal of a low side region to the high side region.
FIG. 1 is a schematic planar view illustrating a general high-voltage semiconductor device.
Referring to FIG. 1, in a high-voltage integration circuit 1, a laterally-diffused metal oxide semiconductor (LDMOS; also known as a lateral double diffused metal oxide semiconductor) device 4 can be surrounded by a high side region 12b, and the LDMOS device 4 can be separated from the high side region 12b by a certain distance by an insulating region 1a. 
FIG. 2 is a cross-sectional view illustrating the related art semiconductor device taken along line A-A′ of FIG. 1, wherein the semiconductor device has a high voltage withstanding Double Reduced Surface Field (RESURF) structure and a level shift function.
Referring to FIG. 2, the semiconductor device includes an N channel RESURF LDMOS field effect transistor (LDMOSFET) (LDMOS region) on the left side and a RESURF separation island region (high side region). The semiconductor device also includes a semiconductor substrate 1 doped with P−, N− epitaxial layers 12a and 12b, a P diffusion region 3 contacted to the P− substrate 1, an N+ buried diffusion region 4, an N diffusion region 5, a P diffusion region 6, an oxide film 7, an aluminum wiring 8, a polysilicon gate 9, an aluminum electrode 10, and polysilicon 11.
The aluminum electrode 10 contacts the N diffusion region 5 and the P diffusion region 6 and is formed at the same location as the RESURF separation island region. The polysilicon 11, to which the same potential as the P diffusion region 3 is applied, serves as a field plate. The N diffusion region 5 and the N+ buried diffusion region 4 form RESURF structures surrounded by the P diffusion regions 3.
In the related art semiconductor device configured as described above, the N channel LDMOSFET is turned on by biasing the gate electrode 9 to positive potential, and current that flows in the P diffusion region 6 induces a potential difference between the electrode 10 and the aluminum wiring 8. By outputting this potential difference, a logic signal applied to the gate 9 may be level-shifted to a high-potential side.
In order to reduce leakage current that flows from a level shift transistor to the high side region 12b, a P− epitaxial layer having low concentration is used for insulation. However, the reduction of the leakage current is limited. In the case of increasing a distance W of the insulating region 1a, an amount of charges for forming a RESURF structure is unbalanced, and thus a breakdown voltage rapidly decreases.
That is, when a P type well is formed to insulate the N channel LDMOSFET from the RESURF separation island region, as the length of the P type well increases, the leakage current is reduced more efficiently, but the breakdown voltage rapidly decreases.